1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a reconfigurable architecture, and more particularly, to processing an exception in a reconfigurable architecture.
2. Description of the Related Art
Traditionally, an apparatus performing an operation is embodied by hardware or software. For example, when a network controller performing a network interface is embodied on a computer chip, the network controller is able to perform only a network interface function defined during fabrication in a factory. After the network controller is fabricated in the factory, changing the function of the network controller is not possible. This is an example of hardware. On the other hand, there is a method of using software. For example, a program for executing a desired function is programmed and the program is executed by a general purpose processor, thereby satisfying a purpose for a user. In the method of using software, a new function may be performed by changing the software after fabricating hardware in a factory. When software is used, various functions may be performed by using a given hardware but there is a drawback of a lower speed than when hardware is exclusively used.
To overcome the problem of the described method of using hardware and software, there is provided a reconfigurable architecture. The reconfigurable architecture can be customized to solve any problem, after device fabrication, and can exploit a large degree of spatially customized computation in order to perform their computation.
FIG. 1 is a diagram illustrating an example of a conventional reconfigurable architecture. In FIG. 1, there is a plurality of arithmetic and logic units (ALUs) 101, 102, 103, 104, and 105. There is a field programmable gate array (FPGA) formed of the plurality of ALUs and a plurality of lines 106 connecting the plurality of ALUs. The FPGA is customized to compute “A*x*x+B*X+C,” as an example. If the operation of “A*x*x+B*X+C” frequently occurs, an FPGA as shown in FIG. 1 is formed for the operation, thereby more quickly performing the operation than the method of using software. Also, a configuration of the FPGA may be changed by applying a current to the lines 106 of the ALUs. Therefore, a configuration for computing another operation may be formed by using the lines. As described above, a reconfigurable architecture is architecture capable of performing a new operation by changing a hardware configuration after fabrication.
In FIG. 1, data is inputted to an ALU one bit at a time. This kind of reconfigurable architecture is called as a fine grained array. If data is inputted to a processing element by units of one word at a time, we call this kind of reconfigurable architecture a coarse grained array (CGA).
FIG. 2 is a diagram illustrating an example of a tightly-coupled coarse grained array architecture utilized by the inventors for describing the present invention.
A coarse grained array 210 includes a plurality of processing elements 211. Each of the plurality of processing elements 211 includes a function unit 212 and a register file 213. The function unit 212 performs computations, and the register file 213 is a group of registers temporarily storing data used by the function unit 212.
A configuration memory 220 stores information associated with a configuration of the coarse grained array 210. According to the configuration stored in the configuration memory 220, the coarse grained array 210 changes a connection state between processing elements included in the coarse grained array 210. A data memory 230 is located outside the coarse grained array 210 and stores data.
A central register file 270 is located outside the coarse grained array 210 and stores values computed by the coarse grained array 210.
A processor using a coarse grained array may include a coarse grained array along with another host processor (not shown). In this case, general instructions are performed by the host processor and instructions requiring repeated execution, such as a loop, may be executed by the coarse grained array. A configuration described above, in which a coarse grained array is separated from the host processor, may be called a loosely-coupled coarse grained array.
On the other hand, the processor shown in FIG. 2 uses selected processing elements 280 which are a part of the plurality of processing elements 211 of the coarse grained array 210, as the host processor. Accordingly, general instructions are performed by the selected processing elements 280, and instructions requiring repeated execution, such as a loop, may be executed by the entire coarse grained array 210 including the selected processing elements 280. A configuration using a part of the plurality of processing elements 211 of a coarse grained array as the host processor may be called as tightly-coupled coarse grained array. In the tightly-coupled configuration, there are two modes, an array mode and an instruction set processor mode. In the array mode, the function units of the coarse grained array 210 execute operations according to the configuration stored in the configuration memory 220. Accordingly, in the array mode, the selected processing elements 280 operate as the part of the coarse grained array 210. In the instruction set processor mode, predetermined function units of the function units of the coarse grained array 210 execute operations. The instruction set processor mode processing may be performed by using an instruction fetch/decoder 260, the central register file 270, and the selected processing elements 280.
If the described tightly-coupled configuration is used, a part of the processing elements in a coarse grained array are used as a host processor and an additional host processor is required. Therefore, a size of the processor may be decreased, and a cost of fabricating the processor may be decreased.
However, when an exception occurs in the above described tightly-coupled coarse grained array architecture, it is difficult to process the exception. An exception is an unexpected event occurring during operation in a computer operating system. As examples of exceptions, there are interrupts, a division by zero, undefined instructions, etc. If an exception occurs, a task currently performed is suspended and the exception must be handled. In the tightly-coupled coarse grained array architecture, exception handling may be performed in the instruction set processor mode. Accordingly, when an exception occurs while the tightly-coupled coarse grained array architecture operates in the array mode, the tightly-coupled coarse grained array architecture has to be switched into the instruction set processor mode to handle the exception. In order to switch the array mode into the instruction set processor mode, a context switch is required. The context is information indicating a current state or a condition of a system, which may include values stored in registers. Namely, in the case an exception occurs when an operation is performed in the array mode, the context of the array mode is stored and the exception is handled. When the exception handling is completed, the stored context has to be restored. Namely, current context values including values stored in all register files and the central register file of the coarse grained array are stored in a memory, and then the exception handling is performed. When the exception handling is completed, the context values stored in the memory are restored and the suspended operation is restarted.
However, as shown in FIG. 2, since the coarse grained array includes a large number of register files, an overhead for storing the values of the register files becomes very great. Namely, since the values stored in the large number of register files have to be stored in the memory, a large amount of time is required. Also, since lines for connecting all of the register files to the data memory 230 are required, the entire design becomes very complicated. As described above, to process an exception requiring a context switch, a considerable amount of overhead occurs in the coarse grained array 210, and there has not been any suggestion to solve this problem.
Also, even though the exception occurs in the instruction set processor mode, there is still a problem created by the context switch.
Accordingly, a method of effectively processing an exception occurring in the tightly-coupled coarse grained architecture is required.